perm filename MPX.LST[MPX,SYS] blob
sn#699496 filedate 1983-02-26 generic text, type T, neo UTF8
COMMENT ⊗ VALID 00002 PAGES
C REC PAGE DESCRIPTION
C00001 00001
C00002 00002 SET SPT=20000 SPECIAL PAGES TABLE BEGINS AT 20000
C00020 ENDMK
C⊗;
SET SPT=20000 ;SPECIAL PAGES TABLE BEGINS AT 20000
LOC 0
;GET HERE ON POWER-ON RESET, I/O BUS RESET AND CONO RESET
;RESET_COND IS SET IF I/O BUS RESET OR POWER-ON RESET BUT IS IGNORED
;BY THIS VERSION OF THE MICROCODE. IT CAN BE CLEARED BY A SUCCESSFUL
;BRANCH ON RESET_COND.
ZAP:
;WE NEED TO CLEAR ALL VBIT ENTRIES AND ALL MAP ENB ENTRIES
000 AR,BR=0/SPEC=5 ;GET CONTROL OF SEL BUS, ETC
;-AR[10-12] → -SEL BUS, AR[13-15] → PADR [20-22]
001 RSWAIT: JUMPIF ~MEM_DONE RSWAIT ;WAIT UNTIL WE GET CONTROL
002 RSVLUP: ~SEL_BUS_REG=¬<AR←-3,7>/SPEC=13
;-SEL BUS←-AR[10-12], CLEAR MCYC MEM DONE
003 MA_HI=<AR←4,7←4> ;MA HI[20-22]←AR[13-15]
004 VBIT=0 ;CLEAR 16 VBIT ENTRIES, FOR DEVICE WHOSE
;# IS IN SEL BUS FOR PGS MA HI[20-22]=0,1...
005 <AR> JUMPIF MASK[0] RSL1;DON'T CLEAR MAP ENB IF AR BIT 0 IS ON
006 MAP_ENB=0 ;CLEAR MAP ENB BIT FOR DEVICE WHOSE # IS IN LOW
;3 BITS OF AR
007 RSL1: AR=≡000101+AR ;INCREMENT AR[10-15] AND [4-9]
010 <AR←3> JUMPIF ~MASK[0] RSVLUP
;IF AR[3] IS OFF, THERE IS MORE TO DO
011 AR=0/SPEC=4 ;RELEASE CONTROL OF SEL BUS, ETC. CLEAR CYC IN PROG
012 CLRBSY: BR=0/SPEC=10 ;CLEAR MIOBC BUSY
013 IDLE: JUMPIF MICRQ_RQ_SYNC MICRQ ;BRANCHING CLEARS MICRQ RQ SYNC
014 JUMPIF MIOBC_BUSY IOBUSY ;BRANCHING CLOCKS MS FROM I
015 JUMPIF TRUE IDLE
;GET HERE ON DATAO MPX OR CONO MPX BITS 22, 23, 30, 31
;MS HAS BEEN LOADED WITH THE I/O BUS DATA EXCEPT FOR BIT 1 WHICH IS
;0 FOR CONO AND 1 FOR DATAO
016 IOBUSY: <MS[0_3]←13.> JUMPIF ~MASK[0] CONO
;JUMP IF MS[1] IS CLEAR (I.E. CONO)
017 <MS[0_3]←12.> JUMPIF ~MASK[0] LDPTP
;JUMP IF MS[0] IS CLEAR (I.E. LOAD PAGE TABLE
;POINTER)
;GET HERE ON DATAO TO LOAD MICROCODE. THE PAGE NUMBER OF THE CORE PAGE THAT
;CONTAINS THE MICROCODE IS IN MS[23-35]
020 MA_HI=<MS[20_35]> ;LOAD UP HI PART OF ADDRESS OF MICROCODE
021 BR=0 ;BR → LO PART OF ADDRESS OF MICROCODE
022 AR=≡40 ;MICROSTORE ADDRESS TO WRITE IN NEXT
023 MLDLP: MA_LO=BR/SPEC=6 ;GET CONTROL OF SEL BUS, ETC. AND BEGIN READ CYC
024 MLRWT: JUMPIF ~MEM_DONE MLRWT ;WAIT UNTIL THE CYCLE IS FINISHED
025 BR=<BR>+1/SPEC=3 ;WRITE MS INTO MICROSTORE AT ADDRESS POINTED TO
;BY AR. COUNT BR TO NEXT MEM ADDRESS.
026 /SPEC=13 ;CLEAR MCYC MEM DONE
027 AR=<AR>+1/SPEC=4 ;COUNT MICROSTORE ADDRESS AND RELEASE SEL BUS, ETC.
030 JUMPIF MICRO_RPE MLPAR
031 <AR←7> JUMPIF ~MASK[0] MLDLP
;THERE IS MORE TO DO UNLESS AR[7] IS CARRIED INTO
032 JUMPIF TRUE CLRBSY ;DONE, CLEAR MIOBC BUSY AND FALL INTO IDLE LOOP
033 MLPAR: /SPEC=12 ;SET MPXERR PAR ERR AND GIVE UP
034 JUMPIF TRUE CLRBSY
;ALL CODE BETWEEN THE TOP OF THE PAGE AND HERE GOES IN THE ROM.
;THAT'S 29 WORDS FOLKS, WE MADE IT!!
LOC 40
;GET HERE ON DATAO WITH I/O BUS BIT 0 OFF. BUS BITS 15-17 ARE THE DEVICE
;WHOSE PAGE TABLE POINTER WE WISH TO SET AND BITS 23-35 ARE THE 13 BITS
;PAGE TABLE POINTER (PAGE NUMBER)
040 LDPTP: AR=<MS[4_19]←-2,17> ;LOAD LOW 4 AR BITS WITH DEVICE CODE
041 ~PTPNT=¬<MS[20_35]> ;WRITE ¬MS[23-35] INTO ¬PTPNT(AR)
042 JUMPIF TRUE CLRBSY ;CLEAR MIOBC BUSY AND FALL INTO IDLE LOOP
043 CONO: <MS[20_35]←11.> JUMPIF MASK[0] ENBMAP
;JUMP IF MS[31] IS SET (I.E. CONO ENABLE MAPPING)
044 <MS[20_35]←10.> JUMPIF MASK[0] CLRMAP
;JUMP IF MS[30] IS SET (I.E. CONO CLEAR MAPPING)
;GET HERE FOR CONO RESET DEVICE WHOSE NUMBER IS IN MS[24-26]
045 AR=<MS[20_35]←-9,7> ;DEVICE TO RESET (FROM MS[24-26])
046 BR,MAP_ENB=0 ;CLEAR MAP ENABLE FOR THE SPECIFIED DEVICE
047 AR=<AR←3,7←3,BR>/SPEC=5 ;GET CONTROL OF SEL BUS, ETC. SET AR 10-12 TO
;DEVICE CODE SPECIFIED IN MS[24-26]
050 AR=≡107000∨AR ;COUNT OUT AFTER ONE DEVICE, BIT 0 USED AS FLAG
;TO AVOID CLEARING MAP ENB
051 JUMPIF TRUE RSWAIT ;GO RESET THE VALID BITS FOR THIS DEVICE
;GET HERE TO CLEAR OR SET THE MAP ENB BIT FOR DEVICE WHOSE NUMBER
;IS IN MS[24-26]
CLRMAP:
052 ENBMAP: AR=<MS[20_35]←-9,7> ;AR GETS DEVICE CODE FROM MS[24-26]
053 MAP_ENB=<MS[20_35]←-4,1>;STORE APPROPRIATE BIT (MS[31]) IN MAP ENB(AR)
;1 FOR ENABLE MAPPING AND 0 FOR DISABLE MAPPING
054 JUMPIF TRUE CLRBSY ;CLEAR MIOBC BUSY AND FALL INTO IDLE LOOP
;GET HERE WHEN SOME DEVICE REQUESTS A MAPPED CYCLE FOR WHICH THERE IS NO
;VALID INFORMATION IN THE MAPPING RAMS
055 MICRQ: ~SEL_BUS_REG=¬<MICRQ_SEL←-4,7>/SPEC=14
;SET SEL BUS REG FROM MICRQ SEL 4,2,1
;CLEAR REQUESTING DEVICE'S MICRQ
056 MA_HI=<PTPNT> ;HI ORDER PART OF MA COMES FROM PAGE TABLE POINTER
;FOR READING, PTPNT IS ADDRESSED BY MICRQ SEL 4,2,1
057 MA_LO=<PADR_MICRO←-7,777>/SPEC=6
;LO ORDER PART OF MA COMES FROM VIRT PAGE NUMBER
;GET CONTROL OF SEL BUS, ETC AND DO READ CYCLE
060 BR=<~VBIT_NEW_BIT> ;ACTIVE LOW BIT TO BE ORED INTO THIS VBIT WORD
061 AR=<PADR_MICRO,3←14.> ;INITIALIZE AR FOR STORING INTO MAPRAM.
;START WITH PADR MICRO 18-19 IN HIGH TWO BITS
062 MRQWT: JUMPIF ~MEM_DONE MRQWT ;WAIT UNTIL WE HAVE CONTROL AND THE WORD IS READ
063 MA_HI=<PADR_MICRO←-7,177>/SPEC=13
;MAHI[20-26]←PADR_MICRO[20-26] AND CLEAR MEM DONE
064 JUMPIF MICRO_RPE PTPAR ;JUMP IF PARITY ERROR IN READING PAGE TABLE
;BRANCHING CLEARS MPXERR MICRO RD PAR ERR
065 VBIT=¬(<~VBIT,,BR>∧BR) ;THAT'S LIKE VBIT=VBIT∨¬BR. VBIT IS ADDRESSED
;BY SEL BUS 4,2,1 AND PADR 20-22.
066 BR=0
067 AR=¬<MS[0_3]←13.,1←13.,AR>
;OR IN WRITE ACCESS BIT (MS[3]) AND
;COMPLEMENT IT AND SECT 18-19
070 <MS[0_3],3←2,BR> JUMPIF ~MASKIS0 NOTPRV
;JUMP IF MS[0-1] NON-ZERO, I.E. NOT A PRIV PAGE
071 ABIT=<MS[0_3]←-1> ;STORE ACCESS BIT (MS[2]) IN THE ABIT RAM
072 MAPSTR: <MS[4_19],17←2,BR> JUMPIF ~MASKIS0 NINCOR
;JUMP IF MS[14-17] NON-ZERO, I.E. NOT IN CORE
073 MAPRAM=<MS[20_35],17777,AR>/SPEC=7
;MASK IN THE MAPPED PAGE NUMBER (MS[23-35]) AND
;STORE IT, THE WRITE ACCESS BIT AND SECT 18-19
;IN THE MAPPING RAM (IT AND ABIT ARE ADDRESSED
;BY SEL BUS 4,2,1 AND PADR 20-26.
;CLEAR STARTED BIT FOR DEVICE IN MICRQ SEL LATCH
074 MAPXIT: /SPEC=4 ;RELEASE CONTROL OF SEL BUS, ETC.
075 JUMPIF TRUE IDLE/SPEC=1 ;RELEASE MICRQ SEL LATCH
;GET HERE IF A PARITY ERROR OCCURRED READING A PAGE TABLE WORD
076 PTPAR: /SPEC=11 ;SET PT PAR ERR FOR DEVICE IN MICRQ SEL 4,2,1
077 /SPEC=4 ;RELEASE CONTROL OF SEL BUS, ETC.
100 JUMPIF TRUE IDLE/SPEC=1 ;RELEASE MICRQ SEL LATCH. THE STARTED LATCH FOR
;THIS DEVICE IS STILL SET, INHIBITING IT FROM
;BEING SEEN FOR FUTURE REQUESTS. RESETTING THE
;DEVICE WILL CLEAR ITS STARTED LATCH.
;GET HERE WHEN BITS 14-17 OF THE PAGE TABLE ENTRY ARE NON-ZERO, INDICATING
;THAT THE PAGE IS NOT IN CORE
101 NINCOR: ABIT=0/SPEC=7 ;SET ACCESS BIT IN ABIT RAM TO ZERO. WILL GET
;ACCESS VIOLATION WHEN THIS CYCLE HAPPENS AGAIN
;CLEAR STARTED BIT FOR DEVICE IN MICRQ SEL LATCH
102 JUMPIF TRUE MAPXIT
;GET HERE WHEN THE PAGE TABLE ENTRY (IN MS) IS NOT A PRIVATE PAGE TYPE.
;BITS MS[0-1] ARE NON-ZERO. 0 1 INDICATES A SHARED PAGE, 1 0 INDICATES
;AN INDIRECT PAGE. 1 1 IS UNDEFINED.
103 NOTPRV: AR=¬<MS[4_19]←-7>/SPEC=4
;AR(15) ← ¬ MS[12], THE ACCESS PERMIT BIT
;RELEASE SEL BUS, ETC.
104 AR=<MS[0_3]←13.,1←13.,AR>
;AR(2) ← MS[3], THE WRITE PERMIT BIT
;****NOTE BR WAS SET ZERO EARLIER****
105 BR=<MS[4_19]←7,77←7,BR> ;BR(3-8) ← MS[14-19]
106 BR=<MS[20_35]←-9,177,BR>
;BR(9-15) ← MS[20-26]
107 BR=≡SPT+BR ;THIS IS THE ADDRESS WE WANT TO READ IN THE SPT
110 MA_LO=BR ;MA_LO=BR(7-15)=MS[18-26]
111 <MS[0_3]←12.> JUMPIF MASK[0] NOTSHR
;JUMP IF MS[0] IS ON, I.E. NOT SHARED
112 MA_HI=<BR←-9,177,BR>/SPEC=6
;MA_HI=BR(0-6), BEGIN READ CYCLE
113 SHRWAT: JUMPIF ~MEM_DONE SHRWAT ;WAIT UNTIL WE GET THE SPT ENTRY
114 MA_HI=<PADR_MICRO←-7,177>/SPEC=13
;MAHI[20-26]←PADR_MICRO[20-26] AND CLEAR MEM DONE
115 JUMPIF MICRO_RPE NPRPAR ;JUMP IF GOT PARITY ERROR WHILE READING SPT
116 AR=¬<PADR_MICRO,3←14.,AR>
;AR(0-1) ← ¬ PADR MICRO 18-19
;AR(2) ← ¬ WRITE PERMIT
;AR(15) ← ACCESS BIT
117 ABIT=AR ;STORE ACCESS BIT IN ABIT RAM
120 BR=0
121 JUMPIF TRUE MAPSTR ;GO STORE MAPRAM AND EXIT
;GET HERE IF WE GOT PARITY ERROR WHILE READING SPECIAL PAGE TABLE ENTRY
;VBIT HAS BEEN TURNED ON, MUST BE TURNED OFF AND PT PAR ERR MUST BE SET
;FOR THE DEVICE IN MICRQ SEL 4,2,1.
122 NPRPAR: BR=¬<~VBIT_NEW_BIT> ;THIS IS THE BIT TO TURN OFF IN VBIT
123 VBIT=¬(<~VBIT,,BR>∨BR) ;THAT'S LIKE VBIT∧¬BR
124 JUMPIF TRUE PTPAR
;GET HERE WHEN THE PAGE TABLE ENTRY (IN MS) IS NOT PRIVATE OR SHARED.
;MS[0] IS A ONE. MS[1] SHOULD BE ZERO FOR AN INDIRECT PAGE TABLE ENTRY.
;MS[1] BEING A ONE IS ILLEGAL AND WILL CAUSE A PAGE NOT IN CORE TYPE TRAP.
125 NOTSHR: <MS[0_3]←13.> JUMPIF ~MASK[0] NINCOR
;JUMP IF MS[1] IS ON, I.E. MS[0-1] = 11
126 MA_HI=<BR←-9,177,BR> ;MA_HI=BR(0-6)
127 BR=<MS[20_35]>/SPEC=6 ;BR = MS[27-35] = PAGE NUMBER TO LOOK UP
;IN NEW PAGE TABLE. BEGIN READ CYCLE.
130 NSHWAT: JUMPIF ~MEM_DONE NSHWAT
131 MA_HI=<PADR_MICRO←-7,177>/SPEC=13
;MAHI[20-26]←PADR_MICRO[20-26] AND CLEAR MEM DONE
132 JUMPIF MICRO_RPE NPRPAR ;JUMP IF GOT PARITY ERROR WHILE READING SPT
133 MA_LO=<BR>/SPEC=4 ;PAGE NUMBER TO LOOK AT IN NEW PAGE TABLE
;RELEASE CONTROL OF SEL BUS, ETC.
134 BR=0
135 <MS[4_19],17←2,BR> JUMPIF ~MASKIS0 NINCOR
;JUMP IF SPT ENTRY POINTS TO PAGE TABLE NOT IN CORE
136 MA_HI=<MS[20_35]>/SPEC=6
;MAHI = MS[23-35] = PAGE NUMBER OF NEW PAGE TABLE
;BEGIN READ CYCLE
137 NSHWA1: JUMPIF ~MEM_DONE NSHWA1
140 MA_HI=<PADR_MICRO←-7,177>/SPEC=13
;MAHI[20-26]←PADR_MICRO[20-26] AND CLEAR MEM DONE
141 JUMPIF MICRO_RPE NPRPAR ;JUMP IF GOT PARITY ERROR WHILE READING INDIR ENTRY
END
SYMBOL TABLE
SPT 020000
ZAP 000000
RSWAIT 000001
RSVLUP 000002
RSL1 000007
CLRBSY 000012
IDLE 000013
MICRQ 000055
IOBUSY 000016
CONO 000043
LDPTP 000040
MLDLP 000023
MLRWT 000024
MLPAR 000033
ENBMAP 000052
CLRMAP 000052
MRQWT 000062
PTPAR 000076
NOTPRV 000103
MAPSTR 000072
NINCOR 000101
MAPXIT 000074
NOTSHR 000125
SHRWAT 000113
NPRPAR 000122
NSHWAT 000130
NSHWA1 000137
ROM LOC=000 OP=4 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=1 BRLD=1
ROM LOC=001 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=1
ROM LOC=002 OP=7 BSEL=0 SPEC=0 S=0 SROT=15 MSIZE=2 MROT=0 M -S CN=1 1111 0 DEST=1 ARLD=0 BRLD=0
ROM LOC=003 OP=0 BSEL=0 SPEC=0 S=0 SROT=4 MSIZE=2 MROT=4 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
ROM LOC=004 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=4 ARLD=0 BRLD=0
ROM LOC=005 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=17 MROT=0 BRCOND=11 BRADDR=7
ROM LOC=006 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=10 ARLD=0 BRLD=0
ROM LOC=007 OP=2 BSEL=0 CONST=177676 M -S CN=0 0110 0 DEST=0 ARLD=1 BRLD=0
ROM LOC=010 OP=1 BSEL=0 SPEC=0 S=0 SROT=3 MSIZE=17 MROT=0 BRCOND=10 BRADDR=2
ROM LOC=011 OP=3 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=1 BRLD=0
ROM LOC=012 OP=5 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=0 BRLD=1
ROM LOC=013 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=15 BRADDR=55
ROM LOC=014 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=2 BRADDR=16
ROM LOC=015 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=13
ROM LOC=016 OP=1 BSEL=0 SPEC=0 S=2 SROT=15 MSIZE=17 MROT=0 BRCOND=10 BRADDR=43
ROM LOC=017 OP=1 BSEL=0 SPEC=0 S=2 SROT=14 MSIZE=17 MROT=0 BRCOND=10 BRADDR=40
ROM LOC=020 OP=0 BSEL=0 SPEC=0 S=4 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
ROM LOC=021 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=0 BRLD=1
ROM LOC=022 OP=2 BSEL=0 CONST=177737 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
ROM LOC=023 OP=4 BSEL=1 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 0101 0 DEST=3 ARLD=0 BRLD=0
ROM LOC=024 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=24
ROM LOC=025 OP=3 BSEL=0 SPEC=0 S=1 SROT=0 MSIZE=17 MROT=0 M -S CN=0 1111 1 DEST=0 ARLD=0 BRLD=1
ROM LOC=026 OP=7 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
ROM LOC=027 OP=3 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=17 MROT=0 M -S CN=0 1111 1 DEST=0 ARLD=1 BRLD=0
ROM LOC=030 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=12 BRADDR=33
ROM LOC=031 OP=1 BSEL=0 SPEC=0 S=0 SROT=7 MSIZE=17 MROT=0 BRCOND=10 BRADDR=23
ROM LOC=032 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=12
ROM LOC=033 OP=6 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
ROM LOC=034 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=12
ROM LOC=035 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
ROM LOC=036 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
ROM LOC=037 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
RAM LOC=040 OP=0 BSEL=0 SPEC=0 S=3 SROT=16 MSIZE=3 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=041 OP=0 BSEL=0 SPEC=0 S=4 SROT=0 MSIZE=17 MROT=0 M -S CN=1 1111 0 DEST=7 ARLD=0 BRLD=0
RAM LOC=042 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=12
RAM LOC=043 OP=1 BSEL=0 SPEC=0 S=4 SROT=13 MSIZE=17 MROT=0 BRCOND=11 BRADDR=52
RAM LOC=044 OP=1 BSEL=0 SPEC=0 S=4 SROT=12 MSIZE=17 MROT=0 BRCOND=11 BRADDR=52
RAM LOC=045 OP=0 BSEL=0 SPEC=0 S=4 SROT=7 MSIZE=2 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=046 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=10 ARLD=0 BRLD=1
RAM LOC=047 OP=4 BSEL=1 SPEC=0 S=0 SROT=3 MSIZE=2 MROT=3 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=050 OP=2 BSEL=0 CONST=070777 M -S CN=1 0001 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=051 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=1
RAM LOC=052 OP=0 BSEL=0 SPEC=0 S=4 SROT=7 MSIZE=2 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=053 OP=0 BSEL=0 SPEC=0 S=4 SROT=14 MSIZE=0 MROT=0 M -S CN=1 0000 0 DEST=10 ARLD=0 BRLD=0
RAM LOC=054 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=12
RAM LOC=055 OP=7 BSEL=0 SPEC=1 S=2 SROT=14 MSIZE=2 MROT=0 M -S CN=1 1111 0 DEST=1 ARLD=0 BRLD=0
RAM LOC=056 OP=0 BSEL=0 SPEC=0 S=7 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=057 OP=4 BSEL=0 SPEC=1 S=2 SROT=11 MSIZE=10 MROT=0 M -S CN=1 0000 0 DEST=3 ARLD=0 BRLD=0
RAM LOC=060 OP=0 BSEL=0 SPEC=0 S=5 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=061 OP=0 BSEL=0 SPEC=0 S=2 SROT=0 MSIZE=1 MROT=16 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=062 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=62
RAM LOC=063 OP=7 BSEL=0 SPEC=0 S=2 SROT=11 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=064 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=12 BRADDR=76
RAM LOC=065 OP=0 BSEL=1 SPEC=0 S=6 SROT=0 MSIZE=17 MROT=0 M -S CN=1 1011 0 DEST=4 ARLD=0 BRLD=0
RAM LOC=066 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=067 OP=0 BSEL=0 SPEC=0 S=2 SROT=15 MSIZE=0 MROT=15 M -S CN=1 1111 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=070 OP=1 BSEL=1 SPEC=0 S=2 SROT=0 MSIZE=1 MROT=2 BRCOND=7 BRADDR=103
RAM LOC=071 OP=0 BSEL=0 SPEC=0 S=2 SROT=17 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=5 ARLD=0 BRLD=0
RAM LOC=072 OP=1 BSEL=1 SPEC=0 S=3 SROT=0 MSIZE=3 MROT=2 BRCOND=7 BRADDR=101
RAM LOC=073 OP=5 BSEL=0 SPEC=0 S=4 SROT=0 MSIZE=14 MROT=0 M -S CN=1 0000 0 DEST=6 ARLD=0 BRLD=0
RAM LOC=074 OP=3 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
RAM LOC=075 OP=1 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=13
RAM LOC=076 OP=6 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
RAM LOC=077 OP=3 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=0 0000 0 DEST=0 ARLD=0 BRLD=0
RAM LOC=100 OP=1 BSEL=0 SPEC=1 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=13
RAM LOC=101 OP=5 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=5 ARLD=0 BRLD=0
RAM LOC=102 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=74
RAM LOC=103 OP=3 BSEL=0 SPEC=1 S=3 SROT=11 MSIZE=17 MROT=0 M -S CN=1 1111 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=104 OP=0 BSEL=0 SPEC=0 S=2 SROT=15 MSIZE=0 MROT=15 M -S CN=1 0000 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=105 OP=0 BSEL=1 SPEC=0 S=3 SROT=7 MSIZE=5 MROT=7 M -S CN=1 0000 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=106 OP=0 BSEL=1 SPEC=0 S=4 SROT=7 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=107 OP=2 BSEL=1 CONST=157777 M -S CN=0 0110 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=110 OP=0 BSEL=1 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 0101 0 DEST=3 ARLD=0 BRLD=0
RAM LOC=111 OP=1 BSEL=0 SPEC=0 S=2 SROT=14 MSIZE=17 MROT=0 BRCOND=11 BRADDR=125
RAM LOC=112 OP=4 BSEL=1 SPEC=1 S=1 SROT=7 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=113 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=113
RAM LOC=114 OP=7 BSEL=0 SPEC=0 S=2 SROT=11 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=115 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=12 BRADDR=122
RAM LOC=116 OP=0 BSEL=0 SPEC=0 S=2 SROT=0 MSIZE=1 MROT=16 M -S CN=1 1111 0 DEST=0 ARLD=1 BRLD=0
RAM LOC=117 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 0101 0 DEST=5 ARLD=0 BRLD=0
RAM LOC=120 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=121 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=72
RAM LOC=122 OP=0 BSEL=0 SPEC=0 S=5 SROT=0 MSIZE=17 MROT=0 M -S CN=1 1111 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=123 OP=0 BSEL=1 SPEC=0 S=6 SROT=0 MSIZE=17 MROT=0 M -S CN=1 1110 0 DEST=4 ARLD=0 BRLD=0
RAM LOC=124 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=14 BRADDR=76
RAM LOC=125 OP=1 BSEL=0 SPEC=0 S=2 SROT=15 MSIZE=17 MROT=0 BRCOND=10 BRADDR=101
RAM LOC=126 OP=0 BSEL=1 SPEC=0 S=1 SROT=7 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=127 OP=4 BSEL=0 SPEC=1 S=4 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=130 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=130
RAM LOC=131 OP=7 BSEL=0 SPEC=0 S=2 SROT=11 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=132 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=12 BRADDR=122
RAM LOC=133 OP=3 BSEL=0 SPEC=1 S=1 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=3 ARLD=0 BRLD=0
RAM LOC=134 OP=0 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 M -S CN=1 1100 0 DEST=0 ARLD=0 BRLD=1
RAM LOC=135 OP=1 BSEL=1 SPEC=0 S=3 SROT=0 MSIZE=3 MROT=2 BRCOND=7 BRADDR=101
RAM LOC=136 OP=4 BSEL=0 SPEC=1 S=4 SROT=0 MSIZE=17 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=137 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=1 BRADDR=137
RAM LOC=140 OP=7 BSEL=0 SPEC=0 S=2 SROT=11 MSIZE=6 MROT=0 M -S CN=1 0000 0 DEST=2 ARLD=0 BRLD=0
RAM LOC=141 OP=1 BSEL=0 SPEC=0 S=0 SROT=0 MSIZE=0 MROT=0 BRCOND=12 BRADDR=122